In manufacturing semiconductor devices, it is important that the devices are free of defects at the time of production, and reliable throughout their use. When defects are found in a die on a wafer, the percentage of usable die decreases, and the profitability of the manufacturer is impacted. More importantly, when a completed semiconductor device fails after it has been installed in a finished product, such as a consumer electronics product, the failure of the semiconductor device can cause the entire product to fail. That is, the failure of a single semiconductor device can render an entire consumer electronics device unusable. Accordingly, it is important that manufacturers of semiconductor devices identify and eliminate defects whenever possible.
Most semiconductor devices are built up using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. The patterning process, such as photolithography, defines the dimensions of the circuit features. Modern semiconductor devices have a significant number of layers formed using complex sequences of process steps. Because problems encountered in the formation of any one layer can render an entire device defective, defective devices are therefore tested to physically locate defects. One goal of testing devices is to identify defective layers, which helps to troubleshoot device processes. After identifying a defective layer, it is also useful to identify the defect, such as by type, location (i.e. by conductor or more specifically within a conductor), etc.
Some semiconductor devices, such as field programmable gate arrays (FPGAs) or complex programmable logic device (CPLDs) (collectively known as programmable logic devices (PLDs)), include extensive routing resources. The routing resources are typically collections of parallel metal lines, also commonly called “conductors,” “interconnect lines,” or “interconnects,” formed using overlapping and isolated metal layers. Insulating layers separate the metal layers, enabling the metal lines to comprise interconnect lines between different layers by making contact through “vias” that extend through the insulating layers. The metal lines in a given layer are minimally spaced to reduce their impact on device area, and are consequently susceptible to short circuits, also called “bridge” defects, that join adjacent wire conductors. These conductors are also exceptionally small in cross section, and are consequently susceptible to open circuits (i.e. points along a given connector that are undesirably electrically disconnected).
Conventional FPGA interconnect designs typically allow some metal lines in certain layers to be probed by components of the circuit (e.g. coupled to a circuit within the integrated circuit to enable a voltage at a node to be captured and read). This ability to probe various points of a conductor of a metal layer makes fault isolation possible for those lines. A group of failure analysis (FA) test patterns called Metal-FA-Pattern is used to test each specific single metal interconnect layer. The Metal-FA-Patterns are used to monitor the quality of the process to form the physical metal layer by using post processed pass/fail results from wafers, and provide quick feed back to process engineers for yield enhancement.
However, some metal lines residing in certain metal layers may not be available to be probed. In many cases, metal layers include conductors having similar lengths, and are formed on separate horizontal and vertical layers. The length of a conductor could be defined by the number of conductor segments coupled between a pair of programmable interconnect points (PIPs). Relatively short conductors (e.g. “double lines” comprising two segments between PIPs could be included in a first pair of metal layers. Similarly, “hex lines” comprising six segments coupled between PIPs could be formed on another pair of horizontal and vertical metal layers, while relatively long conductors extending between the edges of the integrated circuit could be formed on another pair of horizontal and vertical metal layers. While it may be possible to probe nodes of the conductors of certain metal layers, it may not be possible to probe conductors of other layers, depending upon the design of the integrated circuit. However, it is also important to identify failures in the metal layers which cannot be probed.
Accordingly, there is a need for an improved test circuit for and method of identifying the type and location of a defect in a metal layer of an integrated circuit having conductors which cannot be probed.